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Machine Checks Bypass All Interrupt Suppression
Machine check exceptions are the one interrupt that cannot be suppressed, delayed, or latched. Rafal’s 2012 ring-0 escalation, Peterson’s 2018 pop-ss trick, Google Project Zero’s TDX finding, and Schlutoter’s confidential VM leak all got fixed with heavier interrupt suppression. Machine checks bypass all of it. When they arrive, the CPU either handles them immediately or resets. Software, microcode, and hardware interrupt suppression tools like the NRF flag, trap flag, DR7, and SMI latching have no effect on them.
Fuzzing the North Bridge to Generate Machine Checks on Demand
Machine checks occur maybe once per decade on a healthy system. Linux’s /proc/interrupts shows hundreds of interrupts per second, but the machine check row stays at zero. To generate them on demand, Domas built a north bridge fuzzer that randomly flips bits across 24 candidate registers, then attempts a PCI access to a non-existing device. MCA bank registers are sticky and survive system resets, so the fuzzer checks them after each power cycle. After running, it identified two bits that produce machine checks reliably.
Cross-Core Delivery and Preventing System Shutdown
The first two bits only triggered machine checks on the core that generated the PCI abort. That’s useless for exploitation: you can only interrupt your own code. The fuzzer ran for a few hours searching for bit combinations where one core generates the fault but a different core receives the exception. It found three north bridge bits that route machine checks from any core to core zero. With a hijack interrupt descriptor table in place to clear MCA banks before Linux sees them, the system stays up through the attack.
System Management Mode and the Unmodified IDTR
System management mode has existed on x86 for 35 years and operates below the OS and hypervisor. Firmware loads SMM handlers into SM RAM, a locked region that returns 0xFF to ring-zero reads. On AMD, the CPU does not change the IDTR register on SMM entry, so any exception inside SMM dispatches through the untrusted OS interrupt table. The AMD design documents acknowledge this and recommend writing all SMM code without bugs. A divide-by-zero error inside SMM calls the attacker’s handler.
The Fuse Instruction: Hitting a 100-Cycle Attack Window
The attack window opens when EDK2 re-enables machine check handling by writing CR4, and closes 100 cycles later when a LIT instruction loads a safe IDT. A normal PCI MMIO access takes 700 cycles, not nearly enough. Using an 8-byte RAX register instead of the spec-required 4-byte EAX doubles access time to 8,000 cycles. Straddling an unaligned dword boundary splits the access into three 4-byte reads totaling 12,000 cycles. The final read targets a non-existing device, generating the master abort that becomes the machine check.
Code Execution Inside System Management Mode
MC Hammer loads a hijack IDT, times PCI devices to identify the fuse instruction, poisons the north bridge, then fires the fuse and a system management interrupt simultaneously from two threads. The victim thread enters SMM while the fuse instruction is still in flight on the attacking thread. When timing lands correctly, the machine check arrives inside SMM’s 100-cycle window and executes the attacker’s payload at ring-minus-2. Domas used it to dump SM RAM, revealing USB drivers, SPI flash access, a PSP doorbell register, and lock box secrets invisible from ring zero.
Notable Quotes
You must die. No need Christopher “xoreaxeaxeax” Domas · ▶ 7:58
I don’t think anybody’s ever found a way Christopher “xoreaxeaxeax” Domas · ▶ 15:09
Well, that sounds awesome. Christopher “xoreaxeaxeax” Domas · ▶ 32:29
I was following the CPU specs. Christopher “xoreaxeaxeax” Domas · ▶ 31:26
Key Takeaways
- Machine check exceptions bypass all software, microcode, and hardware interrupt suppression on x86 processors.
- Three north bridge bits enable cross-core machine check delivery generated entirely on demand from software.
- AMD SMM entry leaves IDTR unmodified, routing in-SMM exceptions through the untrusted OS interrupt table.
About the Speaker(s)
Christopher “xoreaxeaxeax” Domas is a security researcher focused on firmware, hardware, and low-level processor exploitation. He is known for releasing impractical solutions to non-existent problems: the M/o/Vfuscator single-instruction C compiler, REpsych toolchains for generating images in program control flow graphs, and Turing machines in vi. His security work includes the sandsifter processor fuzzer, the rosenbridge backdoor, the binary visualization tool cantor.dust, and the memory sinkhole privilege escalation exploit.